1. Field of the Invention
The present invention relates to a semiconductor memory device which is suitable for implementing further scaledowns of electronic components and which fixes the potential of word lines or bit lines.
2. Background Art
As a means for reducing variations in the shapes of the memory cells of a semiconductor memory device, a method has been used by which the effects of exposure, etching, and so forth performed during its manufacture on the outermost memory cells of a memory array are eliminated through the utilization of the difference in layout pattern between the memory cells and other circuits caused by forming as dummy memory cells the same layout pattern as that of the memory cells around the perimeter of the memory array. In the following, a method for arranging dummy memory cells in a conventional semiconductor memory device and a method for fixing electric potential will be described with reference to some drawings.
FIG. 8 is a block diagram of the configuration of the conventional semiconductor memory device. The semiconductor memory device of FIG. 8 comprises a memory cell array 1, an input circuit 2, a row selection circuit 3, a column selection circuit 10, and a read/write circuit 11.
The memory cell array 1 comprises memory cells MC(i, j) (i=1 to m and j=1 to n) arranged in matrix form and dummy memory cells DC(i, j) (i=−1 to 0 and j=−1 to n+2, i=m+1 to m+2 and j=−1 to n+2, i=1 to m and j=−1 to 0, and i=1 to m and j=n+1 to n+2) arranged around the memory cells MC(i, j). The memory cells MC(i, j) and the dummy memory cells DC(i, j) are connected to word lines WL(i) (i=−1 to m+2) and bit lines BL(j) (j=−1 to n+2).
The input circuit 2 outputs signals through a row address bus ADDR, a column address bus ADDC, and a control signal bus CONT to the row selection circuit 3, the column selection circuit 10, and the read/write circuit 11 according to signals from a plural-address input bus ADD and a plural-reading/writing-condition input bus MODE.
The row selection circuit 3, which receives the signal from the input circuit 2 via the row address bus ADDR, is connected to the word lines WL(i) (i=−1 to m+2). The row selection circuit 3 makes one of the word lines WL(i) (i=1 to m) transition to a selected state and makes the others transition to non-selected states according to the signal from the row address bus ADDR; the word lines WL(i) (i=−1, 0, m+1, and m+2) to which only the dummy memory cells are connected are fixed to non-selected states at all times.
The column selection circuit 10, which receives the signal from the input circuit 2 via the column address bus ADDC, is connected to the bit lines BLj (j=1 to n) and the read/write circuit 11. The column selection circuit 10 provides electrical continuity between the read/write circuit 11 and the bit line BLj (j=1 to n) through which reading or writing is to be performed of the bit lines BLj (j=1 to n) according to the signal from the column address bus ADDC. The bit lines BLj (j=−1, 0, n+1, and n+2) to which only the dummy memory cells are connected are fixed to non-selected states at all times.
The read/write circuit 11, which receives the signal from the control signal bus CONT, is connected to the column selection circuit 10. At the time of writing, the read/write circuit 11 writes data inputted from a data input/output DATA 10 into the desired memory cell selected by the row selection circuit 3 and the column selection circuit 10 via the column selection circuit 10; at the time of reading, the read/write circuit 11 outputs data from the desired memory cell selected by the row selection circuit 3 and the column selection circuit 10 to the data input/output DATA 10 via the column selection circuit 10.
FIG. 9 is a circuit diagram of the row selection circuit 3 of the semiconductor memory device illustrated in FIG. 8. The row address bus ADDR comprises a row address signal line group ADDRa comprised of “a” pieces of row address selection signal lines, a row address signal line group ADDRb comprised of “b” pieces of row address selection signal lines, and a row address signal line group ADDRc comprised of “c” pieces of row address selection signal lines. Of each row address signal line group, only one of the row address selection signal lines is brought to a selected state (H level) and the other lines are brought to non-selected states (L levels). The inputs of three-input NAND gates NANDR(i) (i=1 to m) are connected to the signal lines constituting the row address signal line groups ADDRa, ADDRb, and ADDRc to perform desired decoding; the outputs of the three-input NAND gates NANDR(i) are connected to the inputs of inverters INVR(i) (i=1 to m). The outputs of the inverters INVR(i) (i=1 to m) are connected to the word lines WL(i) (i=1 to m). And further, the output of individual two-input NAND gates NANDR(i) (i=−1, 0, m+1, and m+2) is connected to one of the two inputs of itself, to the input of individual inverters INVR(i) (i=−1, 0, m+1, and m+2), and to the input of individual inverters INVRR(i) (i=−1, 0, m+1, and m+2). The output of the individual inverters INVRR(i) (i=−1, 0, m+1, and m+2) is connected to the other input of the individual NAND gates NANDR(i) (i=1 to m). The outputs of the inverters INVR(i) (i=−1, 0, m+1, and m+2) are connected to the word lines WL(i) (i=−1, 0, m+1, and m+2). Incidentally, in this example, when at the “H” level, the word lines WL(i) (i=−1, to m+2) are in the selected state, and when at the “L” level, they are in the non-selected state.
Therefore, by using, for example, a potential fixation circuit disclosed in Patent Reference 1 (Japanese Patent Laid-Open No. 63-116455 (Japanese Patent Application No. 61-262324)) in order to maintain the word lines to which only the dummy memory cells are connected in the non-selected state at all times, it is possible to form a configuration in which the gate of transistors constituting the circuits and the gates of transistors constituting the logic gates are not directly connected to power supply lines or ground lines. On account of this, such non-selected states can be realized owing to the fact the even when a gate oxide film has been thinned down due to the shrink of the device, the gate oxide film is not damaged by considerable potential fluctuations caused by static electricity from outside the semiconductor memory device.
The related art semiconductor memory device has problems described below. Generally, in order to shrink the area of a semiconductor memory device, there is a need for circuits which select and drive word lines to have all logic gates and inverters within the regions of memory cells and as a method for eliminating the effects of exposure, etching, and so on performed during manufacture as in the case of its memory array, there is a need to make circuits which fix the potential of dummy word lines to a non-selective potential and the circuits which select and drive the word lines other than the dummy word lines identical with each other and to do identical mask layouts.
However, in the related art semiconductor memory device, the logic gates included in the configuration of the dummy word line potential fixation circuits which fix the potential of the dummy word lines to a non-selective potential are larger in number than those included in the configuration of the word line selection circuits which select and drive the word lines other than the dummy word lines, and therefore there is a problem that since it is difficult to do the mask layout of the circuits within the region of the memory cells, the area of the semiconductor memory device cannot be minimized. In addition, since the dummy word line potential fixation circuits and the word line selection circuits differ in configuration and identical mask layouts cannot be done, there is a problem that the effects of exposure, etching, and so on performed during manufacture cannot be eliminated.